The present invention relates to measuring the surface profile properties of opaque features, and in particular to a metrology procedure to measure dishing that occurs in opaque features surrounded by dielectric features, e.g., after a chemical-mechanical polishing (CMP) step.
The metal interconnect of integrated circuits has conventionally been realized by blanket depositing a layer of metal on a planar insulating surface. Portions of the metal layer are subsequently removed in a photolithographically patterned etching step to form the resulting metal conductors. Conventional integrated circuits have generally employed somewhat resistive metal, such as aluminum, or metal alloys for the metal interconnect. Copper has been chosen as a replacement metal for aluminum in smaller geometry devices. Due to complexities associated with etching copper, it must be patterned in a different manner. Copper is blanket deposited over the wafer that has trenches and vias etched into the dielectric and then it is subjected to chemical mechanical polishing (CMP) to remove the copper from the upper planar surface. The goal is to have a globally planar surface composed of copper and dielectric regions.
FIGS. 1A through 1G show a cut-away view of the conventional fabrication of an aluminum interconnect. As shown in FIG. 1A, a relatively planar surface layer 10, which may be, e.g., a silicon substrate, is covered with a dielectric layer 12, e.g., an oxide layer, which is patterned and etched. An aluminum layer 14, which may be an aluminum alloy, is blanket deposited over the dielectric layer 12, as shown in FIG. 1B. A photoresist layer 16 is deposited over the aluminum layer 14 (FIG. 1C), and is exposed and developed resulting in the structure shown in FIG. 1D. The aluminum layer 14 is then etched, e.g., using a plasma etching technique, resulting in the structure shown in FIG. 1E. The remaining photoresist layer 16 is removed resulting in the structure shown in FIG. 1F. After these steps are completed, the surface is composed of metal lines with near vertical sidewalls above the surface of the dielectric layer 12, as shown in FIG. 1F. Subsequently, dielectric layers are deposited and etched over the metal lines to yield a dielectric layer 18 with a planarized surface, e.g., for the next metal layer, as shown in FIG. 1G.
A major change is being implemented in semiconductor processing by switching from aluminum to copper metallization. Copper is preferred to aluminum due to its lower resistivity and better electromigration resistance. Unfortunately, copper is difficult to etch and the switch from aluminum to copper has forced a change in the basic metallization process. Copper cannot simply be substituted for aluminum in the metallization process because plasma etching of copper is more difficult than plasma etching of aluminum (due to the lack of volatile copper halogen compounds). Additionally, if copper is allowed to directly contact the dielectric materials, it can rapidly diffuse through dielectric materials and contaminate the semiconductor devices.
Thus, a xe2x80x9cdamascenexe2x80x9d process has been developed whereby copper can be used as the interconnect metal. Rather than blanket depositing the interconnect metal on a substantially planar insulating substrate and then etching away parts of the metal layer to leave the conductors, trenches are formed in an insulating material. A composite layer of a diffusion barrier, nucleation layer and copper are then blanket deposited over the entire surface of the insulating substrate such that the trenches are filled. Chemical mechanical polishing is then used to planarize the integrated circuit surface and thereby polish away all the metal that is not in the trenches. The result is metal conductors disposed in trenches and a globally planarized surface.
FIGS. 2A through 2C show a cut-away view of the conventional fabrication of a copper interconnect. As shown in FIG. 2A, a relatively planar surface layer 50, which may be, e.g., a silicon substrate, is covered with a dielectric layer 52, e.g., an oxide layer, which is patterned and etched. The dielectric layer 52 may be patterned and etched in multiple steps in order to produce trenches 54 and via 55. A diffusion barrier layer (not shown), nucleation layer (not shown), and copper layer 56 are blanket deposited over the dielectric layer 52 such that the trenches 54 and via 55 are filled, as shown in FIG. 2B. A chemical mechanical polishing step is then used to planarize the surface of the copper layer 56 (along with the diffusion barrier layer and nucleation layer) with dielectric layer 52, resulting in the structure shown in FIG. 2C.
The ideal copper CMP process removes the copper, nucleation layer and diffusion barrier from the surface of the dielectric while leaving behind the copper, nucleation layer and diffusion barrier in the trenches and contacts or vias. The ideal result would be a globally planarized surface with no vertical height change over the entire wafer surface. FIG. 3 shows the ideal resulting structure with a planar surface composed of a dielectric region 52 and idealized copper region 56. Global planarity is desirable because of the depth of field requirements associated with the lithographic steps. Significant height variations on the surface will compromise the photoresist processing steps and subsequently the etching and metallization processes. Height variations are also symptomatic of undesirable variations in the copper thickness and metal line resistance.
Unfortunately, because of the complexities associated with the CMP process, global planarity is not achievable. An artifact of the CMP processes in copper metallization results from the copper and dielectric material having different polishing rates, resulting in what is known as xe2x80x9cdishing.xe2x80x9d FIG. 4 shows a cut-away side view of the typical resulting structure after the CMP process, in which the surface of the copper region 56a is lower than the surrounding dielectric region 52a. It should be understood that FIG. 4 is for exemplary purposes and is not to scale. Dishing may generally be defined as the maximum height difference between the metal region 56a and the adjacent dielectric region 52a after CMP processing.
Another artifact caused by the CMP process, as known to those of ordinary skill in the art, is xe2x80x9cdielectric erosion,xe2x80x9d i.e., the dielectric regions exhibit a change in height over the surface of the wafer. This variation is related to the local density of metal features. Areas of low metal density exhibit the highest dielectric surface regions whereas areas of high metal density result in lower dielectric surface regions. Dielectric erosion, however, is beyond the scope of this disclosure.
The processing of silicon wafers to form integrated circuit chips requires many complex processing steps. Each step must be carefully monitored and controlled to maximize the quality and yield of the final product. With the imminent replacement of aluminum by copper to form the metallization layers on silicon wafers, new processes and metrology techniques must be developed and implemented to characterize the degree of surface planarization after the CMP step.
Accordingly, what is needed is an economical, reliable, rapid, precise and accurate metrology procedure that will characterize and control the individual process steps in the copper metallization process and specifically that will address dishing that results from certain polishing methods, such as the CMP process.
A metrology process, in accordance with the present invention, measures the dishing of a first feature made of a first material, e.g., an opaque or metal line, that is surrounded by a second material, e.g., a transparent material or dielectric layer, on a production substrate using calibration data. This is done by determining the relative height of the first feature with respect to a second feature where the first feature and the second feature have different dishing rates. The relative height of the first feature with respect to a second feature is then correlated with calibration data to determine the amount of dishing of the first feature. The first and second features can be made of a first material, for example, a metal or metal alloy line containing, e.g., copper, aluminum, or tungsten, while the second material can be a dielectric material. The metrology process is useful, for example, after the metal and dielectric materials undergo a planarization process, e.g., CMP, to approximately planarize the surface of the production substrate. The method utilizes a set of calibration data that correlates the difference in dishing between a first and second feature with the dishing of the first feature. Different sets of calibration data may be utilized based on different parameters used in the planarization process, e.g., a CMP process. It is preferred that the same CMP parameters be used on the calibration samples and the production samples and that the calibration samples have features with approximately the same dishing rates as the features on the production samples.
Determining the relative height of the first feature with respect to the second feature may be done by measuring a first relative height of the first feature with respect to a reference location, measuring a second relative height of the second feature with respect to a reference location and calculating the difference between the first and second relative heights. The composition and thickness of the reference locations must be identical. Any differences in the reference locations will result in measurement errors. The measurements may be at single points, multiple points on a line, or multiple points covering an area. Relative heights are measured using an appropriate metrology device, e.g., a differential interferometer or a laser displacement sensor. The difference between the first and second relative heights, is the relative height of the first feature with respect to the second feature. Additionally, other methods may be used to determine the relative height of the first feature with respect to the second feature, such as directly measuring the relative height of the first feature with respect to the second feature.
The calibration data is produced by initially providing a sample substrate having first and second calibration features that are similar to the features to be measured on the production substrate. The sample substrate is processed in a manner similar to that of the production substrate to produce dishing in the first and second calibration features. Thus, for example, the sample substrate is planarized using a CMP process. The actual dishing of the first and second calibration features is then measured using, e.g., an atomic force microscope, a contact profilometer, or another appropriate device. The difference in dishing between the two calibration features can then be calculated. Finally, the calibration data is produced by relating the difference in dishing between the two calibration features to the actual dishing of the first calibration feature. Additional sets of calibration data may be generated using different parameter settings for the planarization process, e.g., a CMP process. The calibration data for the dishing of the second feature can also be produced by relating the difference in dishing between two calibration features to the actual dishing of the second calibration feature, if desired.
In another embodiment of the present invention, the calibration data is generated in a similar manner, but using a differential interferometer. The sample substrate is processed in a manner similar to that of the production substrate to produce dishing in the first and second calibration features. The sample substrate is then coated with an adequate layer of an opaque material, e.g., 40 nm of platinum. The amount of dishing is not modified by the addition of the opaque material film. Additionally, the opaque film eliminates the phase difference between the high and low regions simplifying the differential interferometer reading. A differential interferometer can then directly measure the actual dishing of the first and second calibration features. The difference in dishing between the two calibration features is then calculated, and calibration data is produced as described.